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Features
* 16-channel GPS Correlator
- 8192 Search Bins with GPS Acquisition Accelerator - Accuracy: 2.5m CEP (2D, Stand Alone) - Time to First Fix: 34s (Cold Start) - Acquisition Sensitivity: -142 dBm (Cold Start, With External LNA) - Tracking Sensitivity: -158 dBm (With External LNA) Utilizes the ARM7TDMI(R) ARM(R) Thumb(R) Processor Core - High-performance 32-bit RISC Architecture - EmbeddedICETM (In-Circuit Emulation) 128 Kbytes Internal RAM 384 Kbytes Internal ROM with u-blox GPS Firmware SuperSense(R) 1.5-bit ADC On-chip Single IF Architecture 2 External Interrupts 24 User-programmable I/O Lines 1 USB Device Port - Universal Serial Bus (USB) 2.0 Full-speed Device - Embedded USB V2.0 Full-speed Transceiver 2 USARTs Master/Slave SPI Interface - 4 External Slave Chip Selects Programmable Watchdog Timer Advanced Power Management Controller (APMC) - Geared Master Clock to Reduce Power Consumption - Sleep State with Disabled Master Clock - Hibernate State with 32.768 kHz Master Clock Real Time Clock (RTC) 1.8V to 3.3V User-definable IO Voltage for Several GPIOs with 5V Tolerance 4 KBytes of Battery Backup Memory 7 mm x 10 mm 96 Pin BGA Package, 0.8 mm Pitch, Pb-free, RoHS-compliant
*
* * * * * * *
ANTARIS4 Single-chip GPS Receiver SuperSense ATR0635
* * * *
* * * *
Benefits
* * * * * * *
Fully Integrated Design With Low BOM No External Flash Memory Required Supports NMEA, UBX Binary and RTCM Protocol for DGPS Supports SBAS (WAAS, EGNOS, MSAS) Up to 4Hz Update Rate Supports A-GPS (Aiding) Excellent Noise Performance
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1. Description
The ATR0635 is a low-power, single-chip GPS receiver, especially designed to meet the requirements of mobile applications. It is based on Atmel's ANTARISTM4 technology and integrates an RF front-end, filtering, and a baseband processor in a single, tiny 7 mm x 10 mm 96 pin BGA package. Providing excellent RF performance with low noise figure and low power consumption. Due to the fully integrated design, just an RF SAW filter, a GPS TCXO and blocking capacitors are required to realize a stand-alone GPS functionality. The ATR0635 includes a complete GPS firmware, licensed from u-blox AG, which performs the GPS operation, including tracking, acquisition, navigation and position data output. For normal PVT (Position/Velocity/Time) applications, there is no need for external Flash- or ROM-memory. The firmware supports e.g. the NMEA protocol (2.1 and 2.3), a binary protocol for PVT data, configuration and debugging, the RTCM protocol for DGPS, SBAS (WAAS, EGNOS and MSAS) and A-GPS (aiding). It is also possible to store the configuration settings in an optional external EEPROM. Due to the integrated ARM7TDMI processor and an intelligent radio architecture, the ATR0635 operates in a complete autonomous mode, utilizing on chip AGC in closed loop operation. For maximum performance, we recommend to use the ATR0635 together with a low noise amplifier (e.g. ATR0610). The ATR0635 supports assisted GPS.
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2. Architectural Overview
2.1 Block Diagram
ATR0635 Block Diagram
PUXTO PURF VDD18 VDDIO VDD_USB VDIG VCC1 VCC2 VBP VBAT18 VBAT LDOBAT_IN LDO_OUT LDO_IN LDO_EN
Figure 2-1.
Power Supply Manager/ PMSS/Logic
AGCO EGC SDI TEST
MO
1
A
RF NRF VCO PLL
D
SIGHI
A D
SIGLO
XTO NXTO
CLK23 XTO X NX GPS Accelerator
APB
RF_ON
Advanced Power Management Controller
XT_IN XT_OUT
SMD Generator
SRAM
RTC
NSHDN NSLEEP
P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2 P1/GPSMODE0 P14/NAADET1 PIO2 P25/NAADET0 P15/ANTON P0/NANTSHORT
PIO2 Controller
SPI
Timer Counter
GPS Correlators
USART2
Special Function
PIO2
P21/TXD2 P22/RXD2
Advanced Interrupt Controller
USART1
P18/TXD1 P31/RXD1
P9/EXTINT0 USB Transceiver Watchdog P16/NEEPROM USB_DP USB_DM USB B R I D G E
ASB
P8/STATUSLED P30/AGCOUT0 P2/BOOT_MODE
Interface to Off-Chip Memory (EBI)
ARM7TDMI
Embedded ICE
DBG_EN NTRST TDI TDO TCK TMS JTAG Reset Controller
SRAM 128K
ROM 384K
PDC2
NRESET
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2.2
General Description
The ATR0635 has been designed especially for mobile applications. It provides high isolation between GPS and cellular bands, as well as very low power consumption. ATR0635 is based on the successful ANTARIS4 technology which includes the ANTARIS high performance SuperSense software in ROM, developed by u-blox AG, Switzerland. ANTARIS provides a proven navigation engine which is used in high-end car navigation systems, automatic vehicle location (AVL), security and surveying systems, traffic control, road pricing, and speed camera detectors, and provides location-based services (LBS) worldwide. The ANTARIS4 chipset has a very low power consumption and comes with a very low BoM for the passive components. Also, as the high performance software SuperSense is available in ROM, no external flash memory is needed. The L1 input signal (fRF) is a Direct Sequence Spread Spectrum (DSSS) signal with a center frequency of 1575.42 MHz. The digital modulation scheme is Bi-Phase-Shift-Keying (BPSK) with a chip rate of 1.023 Mbps.
2.3
PMSS Logic
The power management, startup and shutdown (PMSS) logic ensures reliable operation within the recommended operating conditions. The external power control signals PUrf and PUxto are passed through Schmitt trigger inputs to eliminate voltage ripple and prevent undesired behavior during start-up and shut-down. Digital and analog supply voltages are analyzed by a monitoring circuit, enabling the startup of the IC only when it is within a safe operating range.
2.4
VCO/PLL
The frequency synthesizer features a balanced VCO and a fully integrated loop filter, thus no external components are required. The VCO combines very good phase noise behavior and excellent spurious suppression.The relation between the reference frequency (fTCXO) and the VCO center frequency (fTCXO) is given by: fVCO = fTCXO x 64 = 23.104 MHz x 64 = 1478.656 MHz.
2.5
RF Mixer/Image Filter
Combined with the antenna, an external LNA provides a first band-path filtering of the signal. Atmel's ATR0610 is recommended for the LNA due to its low noise figure, high linearity and low power consumption. The output of the LNA drives a SAW filter, which provides image rejection for the mixer and the required isolation to all GSM bands. The output of the SAW filter is fed into a highly linear mixer with high conversion gain and excellent noise performance.
2.6
VGA/AGC
The on-chip automatic gain control (AGC) stage sets the gain of the VGA in order to optimally load the input of the following analog-to-digital converter. The AGC control loop can be selected for on-chip closed-loop operation or for baseband controlled gain mode.
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2.7 Analog-to-digital Converter
The analog-to-digital converter stage has a total resolution of 1.5 bits. It comprises balanced comparators and a sub-sampling unit, clocked by the reference frequency (fTCXO). The frequency spectrum of the digital output signal (fOUT ), present at the data outputs SIGLO and SIGH1, is 4.348 MHz.
2.8
Baseband
The GPS baseband core includes a 16-channel correlator and is based on an ARM7TDMI ARM processor core with very low power consumption. It has a high-performance 32 bit RISC architecture, uses a high-density 16-bit instruction set. The ARM standard In-Circuit Emulation debug interface is supported via the JTAG/ICE port of the ATR0635. The ATR0635 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBATM Bridge provides an interface between the ASB and the APB. An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI and the on- and off-chip memories without processor intervention. Most importantly, the PDC2 removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. All of the external signals of the on-chip peripherals are under the control of the Parallel I/O Controller (PIO2). The PIO2 Controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO2 Controller in order to define which peripheral signals are connected with off-chip logic. The ATR0635 features a Programmable Watchdog Timer. An Advanced Power Management Controller (APMC) allows for the peripherals to be deactivated individually. Automatic master clock gearing reduces power consumption. A Sleep Mode is available with disabled 23.104 MHz master clock, as well as a Back-up Mode operating 32.768 kHz master clock. A 32.768 kHz Real Time Clock (RTC), together with a buit-in battery back-up SRAM, allows for storage of Almanac, Ephemeris, software configurations to make quick hot- and warm starts. The ATR0635 includes the full high performance firmware (SuperSense), licensed from u-blox AG, Switzerland. Features of the ROM firmware are described in a software documentation available from u-blox AG, Switzerland.
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3. Pin Configuration
3.1 Pinout
Pinning BGA96 (Top View)
Figure 3-1.
1 A B C D E F G H
2
3
4
5
6
7
8
9
10
11
12
ATR0635
Table 3-1.
Pin Name AGCO CLK23 DBG_EN EGC GDIG GND GND GND GND GND GND GNDA GNDA Notes:
ATR0635 Pinout
BGA 96 A4 A8 E8 D4 C5 A6 A9 B11 F5 H8 H12 A3 B1 Pin Type Analog I/O Digital IN Digital IN Digital IN Supply Supply Supply Supply Supply Supply Supply Supply Supply PD Pull Resistor (Reset Value)(1) PIO Bank A Firmware Label I O
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VBAT18 represent the internal power supply of the backup power domain, see section "Power Supply" on page 20. 3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section "Power Supply" on page 20. For operation of the USB interface, supply of 3.0V to 3.6V is required. 4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29, see section "Power Supply" on page 20.
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Table 3-1.
Pin Name GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA LDOBAT_IN LDO_EN LDO_IN LDO_OUT MO NRESET NRF NSHDN NSLEEP NTRST NX NXTO P0 P1 P2 P8 P9 P12 P13 P14 P15 P16 P17 P18 P19 Notes:
ATR0635 Pinout (Continued)
BGA 96 B4 D2 E1 E2 E3 F1 F2 F3 G1 H1 D11 C11 E11 E12 C3 A7 C1 E9 E10 H11 B2 B3 C8 D8 C6 D7 A11 D6 B10 G6 F11 G8 H6 C7 F6 Pin Type Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Digital IN Supply Supply Analog OUT Digital I/O Analog IN Digital OUT Digital OUT Digital IN Analog OUT Analog IN Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O PD Configurable (PD) Configurable (PD) Configurable (PD) PU to VBAT18 Configurable (PU) PU to VBAT18 Configurable (PD) PD Configurable (PU) Configurable (PD) Configurable (PU) Configurable (PU) NANTSHORT GPSMODE0 BOOT_MODE STATUSLED EXTINT0 GPSMODE2 GPSMODE3 NAADET1 ANTON NEEPROM GPSMODE5 TXD1 GPSMODE6 SCK1 SCK1 TXD1 EXTINT1 `0' EXTINT0 NPCS2 `0' `0' PD Open Drain PU Pull Resistor (Reset Value)(1) PIO Bank A Firmware Label I O
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VBAT18 represent the internal power supply of the backup power domain, see section "Power Supply" on page 20. 3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section "Power Supply" on page 20. For operation of the USB interface, supply of 3.0V to 3.6V is required. 4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29, see section "Power Supply" on page 20.
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Table 3-1.
Pin Name P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 PURF PURF PUXTO RF RF_ON SDI SIGHI0 SIGLO0 TCK TDI TDO TEST TMS USB_DM USB_DP VBAT VBAT18(2) VBP VBP VBP VBP VCC1 VCC2 Notes:
ATR0635 Pinout (Continued)
BGA 96 G7 E6 D10 F8 H7 G5 B6 F7 E7 D5 G12 C10 G4 H4 F4 D1 F10 C4 B8 B7 G9 H10 F9 D3 G10 D9 C9 D12 C12 G2 G3 H2 H3 C2 E4 Pin Type Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Digital IN Digital IN Digital IN Analog IN Digital OUT Digital IN Digital OUT Digital OUT Digital IN Digital IN Digital OUT Analog IN Digital IN Digital I/O Digital I/O Supply Supply Supply Supply Supply Supply Supply Supply PU PU PU PD Pull Resistor (Reset Value)(1) Configurable (PD) Configurable (PU) PU to VBAT18 Configurable (PU) Configurable (PU) Configurable (PD) Configurable (PU) Configurable (PU) OH Configurable (PU) PD PU to VBAT18 GPSMODE12 AGCOUT0 RXD1 RXD1 NPCS3 AGCOUT0 PIO Bank A Firmware Label TIMEPULSE TXD2 RXD2 GPSMODE7 GPSMODE8 NAADET0 GPSMODE10 GPSMODE11 RXD2 SCK MOSI MISO NSS SCK MOSI MISO NPCS0 NPCS1 I SCK2 O SCK2 TXD2
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VBAT18 represent the internal power supply of the backup power domain, see section "Power Supply" on page 20. 3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section "Power Supply" on page 20. For operation of the USB interface, supply of 3.0V to 3.6V is required. 4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29, see section "Power Supply" on page 20.
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Table 3-1.
Pin Name VDD_USB(3) VDD18 VDD18 VDD18 VDD18 VDD18 VDDIO
(4)
ATR0635 Pinout (Continued)
BGA 96 A10 H9 G11 F12 B9 E5 B5 H5 A5 A2 A12 B12 A1 Pin Type Supply Supply Supply Supply Supply Supply Supply Supply Supply Analog OUT Analog IN Analog OUT Analog Input Pull Resistor (Reset Value)(1) PIO Bank A Firmware Label I O
VDDIO VDIG X XT_IN XT_OUT XTO Notes:
1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VBAT18 represent the internal power supply of the backup power domain, see section "Power Supply" on page 20. 3. VDD_USB is the supply voltage for following the USB pins: USB_DM and USB_DP, see section "Power Supply" on page 20. For operation of the USB interface, supply of 3.0V to 3.6V is required. 4. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29, see section "Power Supply" on page 20.
3.2
Signal Description
Signal Description
Pin Name RF NRF XTO NXTO X NX XT_IN XT_OUT AGCO EGC AGCOUT0 SDI Type ANALOG IN ANALOG IN ANALOG IN ANALOG IN ANALOG OUT ANALOG OUT ANALOG IN ANALOG OUT ANALOG IO DIGITAL IN DIGITAL OUT DIGITAL IN Active Level Pin Description/Comment Input from SAW filter Inverted input from SAW filter TCXO input (23.104 MHz) Inverted TCXO input (23.104 MHz) XTO interface (capacitor) Inverted XTO interface (capacitor) Oscillator input (32.768 kHz) Oscillator output (32.768 kHz) Automatic gain control analog voltage, connect shunt capacitor to GND Enable external gain control (high = software gain control, low = automatic gain control) Software gain control Software gain control
Table 3-2.
Pin Number RF Section D1 C1
GPS XTAL Section A1 B3 A2 B2 RTC Section A12 B12 A4 D4 G12 C4
Automatic Gain Control, bandwidth setting
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Table 3-2.
Pin Number Boot Section C6 Reset A7 E9 C11 E10 F4 G4, H4 F10
Signal Description (Continued)
Pin Name BOOT_MODE NRESET NSHDN LDO_EN NSLEEP PUXTO PURF RF_ON Type DIGITAL IN DIGITAL IN DIGITAL OUT DIGITAL IN DIGITAL OUT DIGITAL IN DIGITAL IN DIGITAL OUT Active Level Pin Description/Comment Low Low Low High/Low/ Edge Low Low Leave open, internal pull down Reset input; open drain with internal pull-up resistor Shutdown output, connect to LDO_EN (C11) Enable LDO18 Power-up output for GPS XTAL, connect to PUXTO (F4) Power-up input for GPS XTAL Power-up input for GPS radio Power-up output for GPS radio, connect to PURF (G4, H4)
APMC/Power Management
Advanced Interrupt Controller (AIC) A11, B10 USART C10, D10 C7, E6 H6, G7 USB C9 D9 SPI Interface F8 H7 G5 B6 F7, D6, D5 PIO A11, B[6,10], C[6-8,10], D[5-8,10], E[6,7], F[6-8], G[5-8], H[6,7] Configuration B[6,10], D[5,6,8], GPSMODE0-12 F[6-8], H[6,7] G8 GPS D7 G7 STATUSLED TIMEPULSE DIGITAL OUT DIGITAL OUT Status LED GPS synchronized time pulse NEEPROM DIGITAL IN DIGITAL IN Low GPS mode pins Enable EEPROM support SCK MOSI MISO NSS/NPCS0 NPCS1/NPCS2 /NPCS3 DIGITAL I/O DIGITAL I/O DIGITAL I/O DIGITAL I/O DIGITAL OUT SPI clock Master out slave in Master in slave out Slave select Slave select USB_DP USB_DM DIGITAL I/O DIGITAL I/O USB data (D+) USB data (D-) RXD1/RXD2 TXD1/TXD2 SCK1/SCK2 DIGITAL OUT DIGITAL IN DIGITAL I/O USART receive data output USART transmit data input External synchronous serial clock EXTINT0-1 DIGITAL IN External interrupt request
P0 to P31
DIGITAL I/O
-
Programmable I/O ports
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Table 3-2.
Pin Number C8 G5, G6 F11 JTAG Interface E8 F9 G9 G10 H10 H11 Debug/Test C3 D3 B7 B8 A8 C2 E4 G2, G3, H2, H3 A3, B1, B4, D2, E[1-3], F[1-3], G1, H1 Power Digital Part A5 B9, E5, F12, G11,H9 A10 B5, H5 C5 A6, A9, B11, F5, H8, H12 LDO18 E11 E12 LDOBAT D11 D12 C12 LDOBAT_IN VBAT VBAT18 SUPPLY SUPPLY SUPPLY 2.3V to 3.6V 1.5V to 3.6V 1.8V LDOBAT Output LDO_IN LDO_OUT SUPPLY SUPPLY 2.3V to 3.6V 1.8V LDO18 output, max. 80 mA VDIG VDD18 VDD_USB VDDIO GDIG GND SUPPLY SUPPLY SUPPLY SUPPLY SUPPLY SUPPLY Digital supply (radio) 1.8V Core voltage 1.8V USB transceiver supply voltage (3.0V to 3.6V (USB enabled) or 0 to 2.0V (USB disabled)) Variable I/O voltage 1.65V to 3.6V Digital ground (radio) Digital ground MO TEST SIGLO SIGHI CLK23 VCC1 VCC2 VBP ANALOG OUT ANALOG IN DIGITAL OUT DIGITAL OUT DIGITAL OUT SUPPLY SUPPLY SUPPLY IF output buffer Enable IF output buffer Digital IF (data output "Low") Digital IF (data output "High") Digital IF (sample clock) Analog supply 3V Analog supply 3V Analog supply 3V DBG_EN TDO TCK TMS TDI NTRST DIGITAL IN DIGITAL OUT DIGITAL IN DIGITAL IN DIGITAL IN DIGITAL IN Low Debug enable Test data out Test clock Test mode select Test data in Test reset input
Signal Description (Continued)
Pin Name NANTSHORT NAADET0/NAA DET1 ANTON Type DIGITAL IN DIGITAL IN DIGITAL OUT Active Level Pin Description/Comment Low Low Active antenna short detection Input Active antenna detection Input Active antenna power-on Output
Active Antenna Supervision
Power Analog Part
GNDA
SUPPLY
-
Analog Ground
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3.3
Setting GPSMODE0 to GPSMODE12
The start-up configuration of this ROM-based system without external non-volatile memory is defined by the status of the GPSMODE pins after system reset. Alternatively, the system can be configured through message commands passed through the serial interface after start-up. This configuration of the ATR0635 can be stored in an external non-volatile memory like EEPROM. Default designates settings used by ROM firmware if GPSMODE configuration is disabled (GPSMODE0 = 0).
Table 3-3.
Pin
GPSMODE Functions
Function Enable configuration with GPSMODE pins This pin (EXTINT0) is used for FixNOWTM functionality and not used for GPSMODE configuration. GPS sensitivity settings This pin (NAADET1) is used as active antenna supervisor input and not used for GPSMODE configuration. This is the default selection if GPSMODE configuration is disabled. Serial I/O configuration USB power mode General I/O configuration This pin (NAADET0) is used as an active Antenna Supervisor input and not used for GPSMODE configuration General I/O configuration
GPSMODE0 (P1) GPSMODE1 (P9) GPSMODE2 (P12) GPSMODE3 (P13) GPSMODE4 (P14) GPSMODE5 (P17) GPSMODE6 (P19) GPSMODE7 (P23) GPSMODE8 (P24) GPSMODE9 (P25) GPSMODE10 (P26) GPSMODE11 (P27)
GPSMODE12 (P29) Serial I/O configuration
In the case that GPSMODE pins with internal pull-up or pull-down resistors are connected to GND/VDD18, additional current is drawn over these resistors. Especially GPSMODE3 can impact the back-up current. 3.3.1 Enable GPSMODE Pin Configuration Table 3-4. Enable Configuration With GPSMODE Pins
GPSMODE0 (Reset = PD) Description 0(1) 1 Note: Ignore all GPSMODE pins. The default settings as indicated below are used. Use settings as specified with GPSMODE[2, 3, 5 to 8, 10 to 12] 1. Leave open
If the GPSMODE configuration is enabled (GPSMODE0 = 1) and the other GPSMODE pins are not connected externally, the reset default values of the internal pull-down and pull-up resistors will be used.
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3.3.2 Sensitivity Settings Table 3-5.
GPSMODE3 (Fixed PU) 0(1) 0 1 Notes:
(1)
GPS Sensitivity Settings
GPSMODE2 (Reset = PU) Description 0 1 1
(2)
Auto mode (Default ROM value) Fast mode Normal mode High sensitivity
1(2)
(2)
0
(2)
1. Increased back-up current 2. Leave open
For all GPS receivers the sensitivity depends on the integration time of the GPS signals. Therefore there is a trade-off between sensitivity and the time to detect the GPS signal (Time to first fix). The three modes, "Fast Acquisition", "Normal" and "High Sensitivity", have a fixed integration time. The "Normal" mode, recommended for the most applications, is a trade off between the sensitivity and TTFF. The "Fast Acquisition" mode is optimized for fast acquisition, at the cost of a lower sensitivity. The "High Sensitivity" mode is optimized for higher sensitivity, at the cost of longer TTFF. The "Auto" mode adjusts the integration time (sensitivity) automatically according to the measured signal levels. That means the receiver with this setting has a fast TTFF at strong signals, a high sensitivity to acquire weak signals but some times at medium signal level a higher TTFF as the "Normal" mode. These sensitivity settings affect only the startup performance not the tracking performance.
3.4
Serial I/O Configuration
The ATR0635 features a two-stage I/O-message and protocol-selection procedure for the two available serial ports. At the first stage, a certain protocol can be enabled or disabled for a given USART port or the USB port. Selectable protocols are RTCM, NMEA and UBX. At the second stage, messages can be enabled or disabled for each enabled protocol on each port. In all configurations described below, all protocols are enabled on all ports, but output messages are enabled in a way that ports appear to communicate at only one protocol. However, each port will accept any input message in any of the three implemented protocols
Table 3-6.
GPSMODE12 (Reset = PU) 0 0 0 0 1
(2)
Serial I/O Configuration
GPSMODE6 (Reset = PU) 0 0 1(2) 1
(2)
USART1/USB USART2 GPSMODE5 (Output Protocol/ (Output Protocol/ (Reset = PD) Baud Rate (kBaud)) Baud Rate (kBaud)) Messages(1) Information Messages 0(2) 1 0(2) 1 0
(2)
UBX/57.6 UBX/38.4 UBX/19.2 -/Auto NMEA/19.2 NMEA/4.8 NMEA/9.6 UBX/115.2
NMEA/19.2 NMEA/9.6 NMEA/4.8 -/Auto UBX/57.6 UBX/19.2 UBX/38.4 NMEA/19.2
High Medium Low Off High Low Medium Debug
User, Notice, Warning, Error User, Notice, Warning, Error User, Notice, Warning, Error None User, Notice, Warning, Error User, Notice, Warning, Error User, Notice, Warning, Error All
0 0 1(2) 1
(2)
1(2) 1(2) 1 Notes:
(2)
1 0(2) 1
1. See Table 3-7 to Table 3-10 on page 14, the messages are described in the ANTARIS4 protocol specification 2. Leave open
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Both USART ports accept input messages in all three supported protocols (NMEA, RTCM and UBX) at the configured baud rate. Input messages of all three protocols can be arbitrarily mixed. Response to a query input message will always use the same protocol as the query input message. The USB port does only accept NMEA and UBX as input protocol by default. RTCM can be enabled via protocol messages on demand. In Auto mode, no output message is sent out by default, but all input messages are accepted at any supported baud rate. Again, USB is restricted to only NMEA and UBX protocols. Response to query input commands will be given by the same protocol and baud rate as it was used for the query command. Using the respective configuration commands, periodic output messages can be enabled. The following message settings are used in the tables below:
Table 3-7.
NMEA Port UBX Port
Supported Messages at Setting Low
Standard NAV MON GGA, RMC SOL, SVINFO EXCEPT
Table 3-8.
NMEA Port UBX Port
Supported Messages at Setting Medium
Standard NAV GGA, RMC, GSA, GSV, GLL, VTG, ZDA SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, VELNED, TIMEGPS, TIMEUTC, CLOCK
Table 3-9.
NMEA Port
Supported Messages at Setting High
Standard Proprietary NAV MON GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST PUBX00, PUBX03, PUBX04 SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, VELNED, TIMEGPS, TIMEUTC, CLOCK SCHD, IO, IPC, EXCEPT
UBX Port
Table 3-10.
Supported Messages at Setting Debug (Additional Undocumented Message May be Part of Output Data)
Standard Proprietary NAV GGA, RMC, GSA, GSV, GLL, VTG, ZDA, GRS, GST PUBX00, PUBX03, PUBX04 SOL, SVINFO, POSECEF, POSLLH, STATUS, DOP, VELECEF, VELNED, TIMEGPS, TIMEUTC, CLOCK SCHD, IO, IPC, EXCEPT RAW (RAW message support requires an additional license)
NMEA Port
UBX Port
MON RXM
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ATR0635
The following settings apply if GPSMODE configuration is not enabled, that is, GPSMODE = 0 (ROM defaults):
Table 3-11.
Serial I/O Default Setting if GPSMODE Configuration is Deselected (GPSMODE0 = 0)
USART1/USB NMEA 57.6, Auto enabled UBX, NMEA, RTCM NMEA GGA, RMC, GSA, GSV User, Notice, Warning, Error USART2 UBX 57.6, Auto enabled UBX, NMEA, RTCM UBX NAV: SOL, SVINFO MON: EXCEPT User, Notice, Warning, Error
Setting Baud rate (kBaud) Input protocol Output protocol Messages Information messages (UBX INF or NMEA TXT)
3.4.1
USB Power Mode For correct response to the USB host queries, the device has to know its power mode. This is configured via GPSMODE7. If set to bus powered, an upper current limit of 100 mA is reported to the USB host; that is, the device classifies itself as a "low-power bus-powered function" with no more than one USB power unit load.
Table 3-12.
0 1 Note:
USB Power Modes
USB device is bus-powered (maximum current limit 100 mA) USB device is self-powered (default ROM value)
GPSMODE7 (Reset = PU) Description
(1)
1. Leave open
3.4.2
Active Antenna Supervisor The two pins P0/NANTSHORT and P15/ANTON plus one pin of P25/NAADET0/MISO or P14/NAADET1 are always initialized as general purpose I/Os and used as follows: * P15/ANTON is an output which can be used to switch on and off antenna power supply. * Input P0/NANTSHORT will indicate an antenna short circuit, i.e. zero DC voltage at the antenna, to the firmware. If the antenna is switched off by output P15/ANTON, it is assumed that also input P0/NANTSHORT will signal zero DC voltage, i.e. switch to its active low state. * Input P25/NAADET0/MISO or P14/NAADET1 will indicate a DC current into the antenna. In case of short circuit, both P0 and P25/P14 will be active, i.e. at low level. If the antenna is switched off by output P15/ANTON, it is assumed that also input P25/NAADET0/MISO will signal zero DC current, i.e. switch to its active low state. Which pin is used as NAADET (P14 or P25) depends on the settings of GPSMODE11 and GPSMODE10 (see Table 3-14 on page 16).
15
4928C-GPS-06/06
Table 3-13.
Pin
Pin Usage of Active Antenna Supervisor
Usage NANTSHORT Meaning Active antenna short circuit detection High = No antenna DC short circuit present Low = Antenna DC short circuit present Active antenna detection input High = No active antenna present Low = Active antenna is present Active antenna power on output High = Power supply to active antenna is switched on Low = Power supply to active antenna is switched off
P0/NANTSHORT P25/NAADET0/ MISO or P14/NAADET1 P15/ANTON
NAADET
ANTON
Table 3-14.
Antenna Detection I/O Settings
Comment
GPSMODE11 GPSMODE10 GPSMODE8 (Reset = PU) (Reset = PU) (Reset = PU) Location of NAADET 0 0 0 0 1(1) 1(1) 1(1) 1 Note:
(1)
0 0 1(1) 1(1) 0 0 1(1) 1
(1)
0 1
(1)
P25/NAADET0/MISO P25/NAADET0/MISO P14/NAADET1 P14/NAADET1 (Default ROM value) P14/NAADET1 P14/NAADET1 P25/NAADET0/MISO P25/NAADET0/MISO Reserved for further use. Do not use this setting. Reserved for further use. Do not use this setting. Reserved for further use. Do not use this setting.
0 1(1) 0 1(1) 0 1
(1)
1. Leave open
The Antenna Supervisor Software will be configured as follows: 1. Enable Control Signal 2. Enable Short Circuit Detection (power down antenna via ANTON if short is detected via NANTSHORT) 3. Enable Open Circuit Detection via NAADET The antenna supervisor function may not be disabled by GPSMODE pin selection. If the antenna supervisor function is not used, please leave open ANTON, NANTSHORT and NAADET.
16
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3.4.3 External Connections for a Working GPS System Example of an External Connection (ATR0635)
ATR0635
LNA (optional) NC NC NC SIGHI SIGLO CLK23 RF NRF RF_ON PURF NSLEEP PUXTO NC NC NC NC NC NC NC see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 NRESET TMS TCK TDI NTRST TDO DBG_EN P0 - 2 P9 P12 - 17 P19 P23 - 27 P29 - 30 P30/AGCOUT0 SDI NC NC GND analog MO TEST EGC AGCO GND digital GND analog GND GNDD GNDA NSHDN LDO_EN LDO_OUT VDD18 VDIG LDO_IN LDOBAT_IN VBAT18 VBAT +3V (see Power Supply) GND NC: Not connected
Figure 3-2.
SAW
XT_IN 32.768 kHz (see RTC) XT_OUT XTO TCXO 23.104 MHz (see GPS Crystal) NC NC
ATR0610
NXTO
X NX
P8 P20 USB_DM USB_DP P31 P18 P22 P21
STATUS LED TIMEPULSE Optional USB Optional USART 1 Optional USART 2
+3V (see Power Supply) VDDIO +3V (see Power Supply) VDD_USB +3V (see Power Supply) VCC1 VCC2 VBP
+3V (see Power Supply)
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4928C-GPS-06/06
Table 3-15.
Pin Name
Recommended Pin Connections
Recommended External Circuit Internal pull-down resistor; leave open if Antenna Supervision functionality is unused. Internal pull-down resistor; leave open in order to disable the GPSMODE pin configuration feature. Connect to VDD18 to enable the GPSMODE pin configuration feature. Refer to GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 12. Internal pull-down resistor; leave open. Output in default ROM firmware: leave open if not used Internal pull-up resistor; leave open if unused. Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 12. Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 12. Internal pull-down resistor; leave open if Antenna Supervision functionality is unused. Internal pull-down resistor; leave open if Antenna Supervision functionality is unused. Internal pull-up resistor; leave open if no serial EEPROM is connected. Otherwise connect to GND. Internal pull-down resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 12. Output in default ROM firmware: leave open if serial interface is not used.
P0/NANTSHORT P1/GPSMODE0 P2/BOOT_MODE P8/STATUSLED P9/EXTINT0 P12/GPSMODE2/NPCS2 P13/GPSMODE3/ EXTINT1 P14/NAADET1 P15/ANTON P16/NEEPROM P17/GPSMODE5/SCK1 P18/TXD1
Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE P19/GPSMODE6/SIGLO1 definitions in "Setting GPSMODE0 to GPSMODE12" on page 12. P20/TIMEPULSE/SCK2 P21/TXD2 P22/RXD2 P23/GPSMODE7/SCK P24/GPSMODE8/MOSI P25/NAADET0/MISO P26/GPSMODE10/NSS/ NPCS0 P27/GPSMODE11/NPCS1 P29/GPSMODE12/NPCS3 P30/AGCOUT0 P31/RXD1 Output in default ROM firmware: leave open if time pulse feature is not used. Output in default ROM firmware: leave open if serial interface not used. Internal pull-up resistor; leave open if serial interface is not used. Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 12. Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 12. Internal pull-down resistor; leave open if Antenna Supervision functionality is unused. Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 12. Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 12. Internal pull-up resistor; can be left open if the GPSMODE feature is not used. Refer to GPSMODE definitions in "Setting GPSMODE0 to GPSMODE12" on page 12. Internal pull-down resistor; leave open. Internal pull-up resistor; leave open if serial interface is not used.
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3.5 Connecting an Optional Serial EEPROM
The ATR0635 offers the possibility of connecting an external serial EEPROM. The internal ROM firmware supports storing the configuration of the ATR0635 in serial EEPROM. The pin P16/NEEPROM signals the firmware that a serial EEPROM is connected to the ATR0635. The ATR0635's 32-bit RISC processor accesses the external memory via SPI (serial peripheral interface). For best results, use a 32-Kbit 1.8V serial EEPROM such as Atmel's AT25320AY1-1.8. Figure 3-3 shows an example of the serial EEPROM connection. Figure 3-3. Example of a Serial EEPROM Connection
SCK SI SO CS_N
AT25320AY1-1.8
ATR0635 P23/SCK P24/MOSI P25/MISO/NAADET0 P29/NPCS3
HOLD_N WP_N
GND NC
P16/NEEPROM P1/GPSMODE0
GND
GND NSHDN LDO_EN LDO_OUT VDD18 VDDIO
+3V (see Power Supply) LDO_IN LDOBAT_IN NC: Not connected
Note:
The GPSMODE pin configuration feature can be disabled, because the configuration can be stored in the serial EEPROM. VDDIO is the supply voltage for the pins: P23, P24, P25 and P29.
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4928C-GPS-06/06
4. Power Supply
The ATR0635 is supplied with six distinct supply voltages: * The power supplies for the RF part (VCC1, VCC2, VBP) within 2.7V to 3.3V. * VDIG, the 1.8V supply of the digital pins of the RF part (SIGHI, SIGLO and CLK23). VDIG should be connected to VDD18. * VDD18, the nominal 1.8V supply voltage for the core, the I/O pins, the memory interface and the test pins and all GPIO pins not mentioned in next item. * VDDIO, the variable supply voltage within 1.8V to 3.6V for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29. In input mode, these pins are 5V input tolerant. * VDD_USB, the power supply of the USB pins: USB_DM and USB_DP. * VBAT18 to supply the backup domain: RTC, backup SRAM and the pins NSLEEP, NSHDN, LDO_EN, VBAT18, P9/EXTIN0, P13/EXTINT1, P22/RXD2 and P31/RXD1 and the 32kHz oscillator. In input mode, the four GPIO-pins are 5V input tolerant.
20
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4928C-GPS-06/06
ATR0635
Figure 4-1. Connecting Example: Separate Power Supplies for RF and Digital Part Using the Internal LDOs
ATR0635 internal
VCC1 2.7V to 3.3V VCC2 RF VBP VDIG 2.3V to 3.6V LDO_IN NSHDN LDO_EN LDO_OUT ldoin ldoen ldoout LDO18
VDD18
Core
1 F (X7R)
VDDIO
1.8V to 3.3V variable I/O domain
LDOBAT
ldobat_in LDOBAT_IN 1.5V to 3.6V VBAT VBAT18 vbat vbat18
1 F (X7R)
VDD
RTC backup memory
0V or 3V to 3.6V
VDDUSB
USB SM and transceiver
The ATR0635 contains a built in low dropout voltage regulator LDO18. This regulator can be used if the host system does not provide the core voltage VDD18 of 1.8V nominal. In such case, LDO18 will provide a 1.8V supply voltage from any input voltage VDD between 2.3V and 3.6V. The LDO_EN input can be used to shut down VDD18 if the system is in standby mode. If the host system does supply a 1.8V core voltage directly, this voltage has to be connected to the VDD18 supply pins of the Core. LDO_EN must be connected to GND. LDO_IN can be connected to GND. LDO_OUT must not be connected. A second built in low dropout voltage regulator LDOBAT provides the supply voltage for the RTC and backup SRAM from any input voltage VBAT between 1.5V and 3.6V. The backup battery delivers the supply current if LDOBAT_IN is not powered.
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4928C-GPS-06/06
The RTC section will be initialized properly if VDD18 is supplied first to the ATR0635. If VBAT is applied first, the current consumption of the RTC and backup SRAM is undetermined. Figure 4-2. Connecting Example: Common Power Supplies for RF and Digital Part Using the Internal LDOs
ATR0635 internal
VCC1 VCC2 RF VBP VDIG LDO18
2.7V to 3.3V NSHDN
LDO_IN LDO_EN LDO_OUT
ldoin ldoen ldoout
VDD18
1 F (X7R)
VDDIO
Core
1.8V to 3.3V variable IO domain
LDOBAT
ldobat_in LDOBAT_IN 1.5V to 3.6V VBAT VBAT18 vbat vbat18
1 F (X7R)
VDD
RTC backup memory
0V or 3V to 3.6V
VDDUSB
USB SM and transceiver
The USB Transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND (internal pull-down resistors). The USB Transceiver is enabled if VDD_USB within 3.0V and 3.6V.
22
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ATR0635
Figure 4-3. Connecting Example: Separate Power Supplies for RF and Digital Part Using 1.8V from Host System
ATR0635 internal
VCC1 2.7V to 3.3V VCC2 RF VBP VDIG LDO18
LDO_IN LDO_EN LDO_OUT
ldoin ldoen ldoout
1.65V to 1.95V VDD18
Core
VDDIO
1 F (X7R)
2.3V to 3.6V 1.5V to 3.6V LDOBAT_IN VBAT VBAT18
1.8V to 3.3V variable I/O domain
LDOBAT
ldobat_in vbat vbat18
1 F (X7R)
VDD
RTC backup memory
0V or 3V to 3.6V
VDDUSB
USB SM and transceiver
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4928C-GPS-06/06
Figure 4-4.
Connecting Example: Power Supply from USB Using the Internal LDOs
ATR0635 internal
VCC1 VCC2 RF VBP VDIG LDO18
LDO_IN NSHDN LDO_EN LDO_OUT
ldoin ldoen ldoout
VDD18
Core
1 F (X7R)
VDDIO
1.8V to 3.3V variable I/O domain
LDOBAT
ldobat_in LDOBAT_IN 1.5V to 3.6V VBAT VBAT18 vbat vbat18
1 F (X7R)
VDD
RTC backup memory
USB-VSB 5V
External LDO 3.0V to 3.3V
VDDUSB
USB SM and transceiver
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4928C-GPS-06/06
ATR0635
5. Crystals
The ATR0635 requires a GPS TCXO. The reference frequency is 23.104 MHz. By connecting an optional RTC crystal, different power modes are available. The reference frequency is 32.768 kHz.
5.1
GPS
Figure 5-1. Equivalent Application Examples Using a GPS TCXO (See Table 5-1 on page 26)
22 pF A1 12 pF TCXO 4.7 pF Do not connect B3 XTO NXTO
A2 B2
X NX
12 pF 22 pF TCXO 4.7 pF Do not connect
A1 XTO B3 NXTO
A2 B2
X NX
Figure 5-2.
Application Example Using an External Reference Frequency and Balanced Inputs (See Table 5-2 on page 26)
1:1 Vin
A1 B3
XTO NXTO
A2 Do not connect B2
X NX
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4928C-GPS-06/06
Table 5-1.
Parameter
Specification of GPS TCXOs Appropriate for the Application Example Shown in Figure 5-1 on page 25
Comment Nominal frequency referenced to 25C Over operating temperature range Including calibration, temperature, soldering and ageing effects Operating temperature range DC coupled clipped sine wave Operating range Tolerable load capacitance 0.8 10 1.5 V pF -40.0 Min Typ Max Units
Frequency Characteristics Nominal Frequency 23.104 0.5 8 +85.0 MHz ppm ppm C
Frequency deviation Temperature range Electrical Output waveform Output voltage (peak-to-peak) Output load capacitance
Table 5-2.
Parameter
Specification of an External Reference Signal for the Application Example Shown in Figure 5-2 on page 25
Comment Min Typ 23.104 Sine wave or clipped sine wave Voltage peak-to-peak 0.6 0.9 1.2 V Max Units MHz
Signal Characteristics Nominal Frequency Waveform Amplitude
5.2
RTC Oscillator
Crystal Connection
ATR0635 internal
XT_IN 32 kHz Crystal Oscillator XT_OUT
Figure 5-3.
32.768 kHz 50 ppm
32.768 kHz clock
RTC
C
C
C = 2 x Cload, Cload can be derived from the crystal datasheet. Maximum value for C is 25 pF.
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6. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Operating temperature Storage temperature Analog supply voltage Digital supply voltage RF DC supply voltage core DC supply voltage VDDIO domain DC supply voltage USB DC supply voltage LDO18 DC supply voltage LDOBAT DC supply voltage VBAT VCC1, VCC2, VBP VDIG VDD18 VDDIO VDD_USB LDO_IN LDOBAT_IN VBAT P0, P15, P30, XT_IN, TMS, TCK, TDI, NTRST, DBG_EN, LDO_EN, NRESET USB_DM, USB_DP Pins Symbol Top Tstg VCC VDIG VDD18 VDDIO VDD_USB LDO_IN LDOBAT_IN VBAT Min -40 -55 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max +85 +125 +3.7 +3.7 +1.95 +3.6 +3.6 +3.6 +3.6 +3.6 Unit C C V V V V V V V V
Digital input voltage
-0.3
+1.95
V
Digital input voltage Digital input voltage Note:
-0.3
+3.6 +5.0
V V
P1, P2, P8, P9, P12 to -0.3 P14, P16 to P27, P29, P31 Minimum/maximum limits are at +25C ambient temperature, unless otherwise specified.
7. Handling
The ATR0635 is an ESD-sensitive device. The current ESD values are to be defined. Observe proper precautions for handling.
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4928C-GPS-06/06
8. Operating Range
Parameters Analog supply voltage RF Digital supply voltage RF Digital supply voltage core Digital supply voltage VDDIO domain(1) Digital supply voltage USB(2) DC supply voltage LDO18 DC supply voltage LDOBAT DC Supply voltage VBAT Supply voltage difference (V = VCC - VDIG) Temperature range Input frequency Reference frequency GPS XTAL Reference frequency RTC Notes: Pins VCC1, VCC2, VBP VDIG VDD18 VDDIO VDD_USB LDO_IN LDOBAT_IN VBAT Symbol VCC VDIG VDD18 VDDIO VDD_USB LDO_IN LDOBAT_IN VBAT V Temp fRF fTCXO fXTC -40 1575.42 23.104 32.768 Min 2.70 1.65 1.65 1.65 3.0 2.3 2.3 1.5 0.80 +85 1.8 1.8 1.8/3.3 3.3 Typ Max 3.30 1.95 1.95 3.6 3.6 3.6 3.6 3.6 Unit V V V V V V V V V C MHz MHz KHz
1. VDDIO is the supply voltage for the following GPIO-pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 2. Values defined for operating USB Interface. Otherwise VDD_USB may be connected to ground.
9. Electrical Characteristics
If no additional information is given in column Test Conditions, the values apply to temperature range from -40C to +85C. No. 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.1 2.2 2.3 Notes: Parameters RF Front-end Output frequency Input impedance (balanced) Mixer conversion gain Mixer noise figure (SSB) Maximum total gain Total noise figure (SSB) VGA/AGC Minimum gain Maximum gain Control-voltage sensitivity VAGCO = 1.0V VAGCO = 2.2V VAGCO = 2.2V VAGCO = 1.0V GVGA,min GVGA,max NVGA,min NVGA,max 0 70 6.6 150 dB dB dB/V dB/V VAGCO = 2.2V fTXCO = 23.104 MHz fRF = 1575.42 MHz C3 D1, C1 C3 C3 fIF Z11 GMIX NFMIX Gmax_tot NFtot 96.764 10 - j80 10 6 90 6.8 MHz dB dB dB dB Test Conditions Pin Symbol Min Typ Max Unit
1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core voltage VDD18. 2. The LDOBAT is a built in low dropout voltage regulator, which provides the supply voltage VBAT18 for the RTC, backup SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN falls below 1.5V. 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT. 4. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)
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9. Electrical Characteristics (Continued)
If no additional information is given in column Test Conditions, the values apply to temperature range from -40C to +85C. No. 2.4 2.5 2.6 3 3.1 3.2 4 4.1 4.2 4.3 4.4 5 5.1 5.2 Parameters AGC cut-off frequency AGC cut-off frequency Gain-control output voltage PMSS Voltage level power-on Voltage level power-off LDO18
(1)
Test Conditions Cext = open Cext = 100 pF
Pin A4 A4 A4
Symbol f3dB_AGC f3dB_AGC VAGCO
Min
Typ 250 33
Max
Unit kHz kHz
0.9
2.3
V
F4, G4, H4 F4, G4, H4 LDO_OUT LDO_OUT After startup, no load Standby mode (LDO_EN = 0) VBAT18 After startup (sleep/backup mode), at room temperature After startup (backup mode and LDOBAT_IN = 0V), at room temperature After startup (normal mode), at room temperature
VPU,on VPU,off
1.3 0.5 1.65 1.8 1.95 80 80 1 5
V V V mA A A
Output voltage Output current Current consumption Current consumption LDOBAT(2) Output voltage(3) Current consumption LDOBAT_IN(4) Current consumption VBAT
1.65
1.8
1.95 15
V A
5.3
10
A
5.4 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Notes:
Current consumption Core DC supply voltage VDD18 DC supply voltage VDDIO Low-level input voltage VDD18 domain High-level input voltage VDD18 domain Schmitt trigger threshold rising Schmitt trigger threshold falling Schmitt trigger hysteresis
1.5
mA
VO,18 VO,IO VDD18 = 1.65V to 1.95V VDD18 = 1.65V to 1.95V VDD18 = 1.65V to 1.95V VDD18 = 1.65V to 1.95V VDD18 = 1.65V to 1.95V CLK23 CLK23 CLK23 VIL,18 VIH,18 Vth+,CLK23 Vth-,CLK23 Vhyst,CLK23
0 0 -0.3 0.7 x VDD18
VDD18 VDDIO 0.3 x VDD18 VDD18 + 0.3 0.7 x VDD18
V V V V V V
0.3 x VDD18 0.3 0.55
V
1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core voltage VDD18. 2. The LDOBAT is a built in low dropout voltage regulator, which provides the supply voltage VBAT18 for the RTC, backup SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN falls below 1.5V. 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT. 4. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)
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9. Electrical Characteristics (Continued)
If no additional information is given in column Test Conditions, the values apply to temperature range from -40C to +85C. No. 6.8 6.9 6.10 6.11 6.12 6.13 6.14 Parameters Schmitt trigger threshold rising Schmitt trigger threshold falling Low-level input voltage VDDIO domain High-level input voltage VDDIO domain Low-level input voltage VBAT18 domain High-level input voltage VBAT18 domain Low-level input voltage USB High-level input voltage USB Low-level output voltage VDD18 domain High-level output voltage VDD18 domain Low-level output voltage VDDIO domain High-level output voltage VDDIO domain Low-level output voltage VBAT18 domain High-level output voltage VBAT18 domain Low-level output voltage USB High-level output voltage USB Test Conditions VDD18 = 1.65V to 1.95V VDD18 = 1.65V to 1.95V VDDIO = 1.65V to 3.6V VDDIO = 1.65V to 3.6V VBAT18 = 1.65V to 1.95V VBAT18 = 1.65V to 1.95V VDD_USB = 3.0V to 3.6V VDD_USB = 3.0V to 3.6V 39 source resistance + 27 external series resistor IOL = 1.5 mA, VDD18 = 1.65V IOH = -1.5 mA, VDD18 = 1.65V IOL = 1.5 mA, VDDIO = 3.0V IOH = -1.5 mA, VDDIO = 3.0V IOL = 1 mA IOH = -1 mA IOL = 2.2 mA, VDD_USB = 3.0V to 3.6V, 27 external series resistor IOH = 0.2 mA, VDD_USB = 3.0V to 3.6V, 27 external series resistor P9, P13, P22, P31 P9, P13, P22, P31 DP, DM A11, B10, C10, D10 A11, B10, C10, D10 C9, D9 Pin NRESET NRESET Symbol Vth+,NRESET Vth-,NRESET VIL,IO VIH,IO VIL,BAT VIH,BAT VIL,USB VIH,USB VOL,18 VOH,18 VOL,IO VOH,IO VOL,BAT VOH,BAT VOL,USB 1.2 VDDIO - 0.5 0.4 VDD18 - 0.45 0.4 Min 0.8 0.46 -0.3 1.46 -0.3 1.46 -0.3 Typ Max 1.3 0.77 +0.41 5.0 +0.41 5.0 +0.8 Unit V V V V V V V
6.15
C9, D9
2.0
3.6
V
6.16 6.17 6.18 6.19 6.20 6.21
0.4
V V V V V V
6.22
0.3
V
6.23
DP, DM
VOH,USB ILEAK ICAP
2.8
V
6.24 6.25 6.26 Notes:
Input-leakage current VDD18 = 1.95V (standard inputs and I/Os) VIL = 0V Input capacitance Input pull-up resistor NRESET -40C to +85C A7
-1
+1 10
A pF k
RPU
0.7
1.8
1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core voltage VDD18. 2. The LDOBAT is a built in low dropout voltage regulator, which provides the supply voltage VBAT18 for the RTC, backup SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN falls below 1.5V. 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT. 4. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)
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9. Electrical Characteristics (Continued)
If no additional information is given in column Test Conditions, the values apply to temperature range from -40C to +85C. No. 6.27 6.28 6.29 6.30 Parameters Input pull-up resistors TCK, TDI, TMS Test Conditions -40C to +85C Pin G9, H10, G10 A11, B10, C10, D10 E8, H11 F10, C8, F11, G12 Symbol RPU RPU RPD RPD Min 7 100 7 100 Typ Max 18 235 18 235 Unit k k k k
Input pull-up resistors P9, -40C to +85C P13, P22, P31 Input pull-down resistors -40C to +85C DBG_EN, NTRST, RF_ON Input pull-down resistors P0, P15, P30 -40C to +85C
6.31
Configurable input pull-up resistors P1, P2, P8, P12, -40C to +85C P14, P16 to P21, P23 to P27, P29 Configurable input pull-down resistors P1, P2, -40C to +85C P8, P12, P14, P16 to P21, P23 to P27, P29 Configurable input pull-up resistor USB_DP (idle -40C to +85C state) Configurable input pull-up resistor USP_DP -40C to +85C (operation state) Input pull-down resistors USB_DP, USB_DM -40C to +85C C9
RCPU
50
160
k
6.32
RCPD
40
160
k
6.33
RCPU
0.9
1.575
k
6.34
C9
RCPU RPD
1.425
3.09
k
6.35 Notes:
C9, D9
10
500
k
1. The LDO18 is a built in low dropout voltage regulator, which can be used if the host system does not provide the core voltage VDD18. 2. The LDOBAT is a built in low dropout voltage regulator, which provides the supply voltage VBAT18 for the RTC, backup SRAM, P9, P13, P22, P31, NSLEEP and NSHDN. The LDOBAT voltage regulator switches in battery mode if LDOBAT_IN falls below 1.5V. 3. Supply voltage VBAT18 for backup domain is generated internally by the LDOBAT. 4. If no current is caused by outputs (pad output current as well as current across internal pull-up resistors)
10. Power Consumption
Mode Sleep Shutdown Normal Note: Conditions At 1.8V, no CLK23 RTC, backup SRAM and LDOBAT Satellite acquisition Normal tracking on 6 channels with 1 fix/s; each additional active tracking channel adds 0.5 mA All channels disabled 1. Specified value only Typ 0.065 40 29 26
(1)
Unit
0.007(1) mA
31
4928C-GPS-06/06
11. Ordering Information
Extended Type Number ATR0635-7KQY ATR0635-EK1 ATR0635-DK1 Package BGA96 MPQ 3000 1 1 Remarks 7 mm x 10 mm, 0.8 mm pitch, Pb-free, RoHS-compliant Evaluation kit/Road test kit Design kit including design guide and PCB Gerber files
12. Package Information
Package: BGA96 Dimensions in mm
n 0.08 m n 0.15 m
2.
C BA
0.40.05
A1 Corner Top View 1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F G H Bottom View A1 Corner 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H
70.05
5.6
0.8
Pin A1 Laser Marking
0.8
A
8.8 100.05 0.750.05
technical drawings according to DIN specifications
B
0.08 C
Drawing-No.: 6.580-5005.01-4
0.1 C
Seating plane 3.
C
Note: 1. All dimensions and tolerance conform to ASME Y 14.5M-1994 2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C 3. Primary datum C and seating plane are defined by the spherical crowns of the solder balls 4. The surface finish of the package shall be EDM CHARMILLE #24 - #27 5. Unless otherwise specified tolerance: Decimal 0.05, Angular 2 5. Raw ball diameter: 0.4 mm ref.
32
ATR0635
4928C-GPS-06/06
0.260.04
Issue: 2; 31.05.06 1.4 max 0.30.05
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4928C-GPS-06/06

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